
191
XMEGA A [MANUAL]
8077I–AVR–11/2012
Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bit 3:2 – COMPINTLVL[1:0]: Compare Match Interrupt Enable
These bits enable the RTC compare match interrupt and select the interrupt level, as described in
“Interrupts andINTFLAGS register is set.
Bit 1:0 – OVFINTLVL[1:0]: Overflow Interrupt Enable
set.
17.3.4 INTFLAGS
– Interrupt Flag register
Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to zero
when this register is written.
Bit 1 – COMPIF: Compare Match Interrupt Flag
This flag is set on the next count after a compare match condition occurs. It is cleared automatically when the RTC
compare match interrupt vector is executed. The flag can also be cleared by writing a one to its bit location.
Bit 0 – OVFIF: Overflow Interrupt Flag
This flag is set on the next count after an overflow condition occurs. It is cleared automatically when the RTC overflow
interrupt vector is executed. The flag can also be cleared by writing a one to its bit location.
17.3.5 TEMP – Temporary register
Bit 7:0 – TEMP[7:0]: Temporary bits
This register is used for 16-bit access to the counter value, compare value, and TOP value registers. The low byte of the
16-bit register is stored here when it is written by the CPU. The high byte of the 16-bit register is stored when the low byte
Bit
7
65
43
210
+0x03
–
COMPIF
OVFIF
Read/Write
R
R/W
Initial Value
0
00
000
Bit
7
65
43
2
1
0
+0x04
TEMP[7:0]
Read/Write
R/W
Initial Value
0